High-resolution frequency-synthesized signal generators are typically constructed using a single integrated circuit (IC) and additional support components for each channel, requiring significant board space and cost. In order to synchronize the output clock signals of respective first and second signal generators, an exclusive-OR operation may be performed on the corresponding first and second clock signals to provide a signal having a pulse width corresponding to the phase offset between the first and second clock signals. The exclusive-OR signal may be low pass filtered and the phase offset subsequently measured using an analog-to-digital converter (ADC). The measured phase offset may be used to adjust the phase of the clock signals. This procedure may be repeated for each output clock signal to be synchronized. The circuitry may be built using field programmable gate arrays (FPGAs).
However, a disadvantage of the above described solution is that analog components are required externally of the FPGA. That is, filters and ADCs are necessary. Moreover, since the measured phase offset value may be noisy, a substantial amount of averaging may be necessary to obtain acceptable resolution. The process may therefore be slow. Also, as the pulse width of the exclusive-OR signal narrows, the rise and fall characteristics of an output driver may consequently become significant, tending to skew the results. Still further, to reduce the need of expensive analog components, a single ADC may typically be used by the various channels in a time sharing manner, further slowing the process
There is therefore a need to efficiently synchronize multiple signal generators without analog components, to provide less expensive and smaller design solutions.